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rev. a a ad8186/ad8187 480 mhz single-supply (5 v) t riple 2:1 multiplexers information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. features fully buffered inputs and outputs fast channel-to-channel switching: 4 ns single-supply operation (5 v) high speed: 480 mhz bandwidth (? db) 2 v p-p >1600 v/ s (g = +1) >1500 v/ s (g = +2) fast settling time of 7 ns to 0.1% low current: 19 ma/20 ma excellent video specifications (r l = 150 ) 0.05% differential gain error 0.05 differential phase error low glitch all hostile crosstalk ?4 db @ 5 mhz ?2 db @ 100 mhz high off isolation of ?5 db @ 5 mhz low cost fast, high impedance disable feature for connecting multiple outputs logic-shifted outputs applications switching rgb in lcd and plasma displays rgb video switchers and routers functional block diagram in0a d gnd v ref out 0 out 1 out 2 in1a in2a in2b in1b in0b v cc v ee v ee v ee v cc oe sel a/ b v ee v cc v cc v cc v ee dv cc logic 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad8186/ad8187 0 1 2 select enable table i. truth table sel a/ b oe out 00 high z 10 high z 11in a 01in b general description the ad8186 (g = +1) and ad8187 (g = +2) are high speed, single-supply, triple 2-to-1 multip lexers. they offer ? db large signal bandw idth of over 480 mhz along with a slew rate in excess of 1500 v/ s. with better than ?0 db of all hostile crosstalk and ?5 db off isolation, they are suited for many high speed appli- ca tions. the differential gain and differential phase error of 0.05% and 0.05 , along with 0.1 db flatness to 85 mhz, make the ad8186 and ad8187 ideal for professional and component video multiplexing. they offer 4 ns switching time, making them an excellent choice for switching video signals while consuming less than 20 ma on a single 5 v supply (100 mw ). both devices have a high speed dis able feature that sets the outputs into a high impedance state. t his allows the building of larger input arrays while minimizing off channel output loading. the devices are offered in a 24-lead tssop package. time (ns) output voltage (v) 05 10 6.0 5.5 input voltage (v) 2.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 ?.5 ?.0 3.5 4.0 2.0 1.5 1.0 input output 15 20 5.0 25 figure 1. ad8187 video amplitude pulse response, v out = 1.4 v p-p, r l = 150 ?
rev. a e2e ad8186/ad8187especifications (t a = 25 c; ad8186: v s = 5 v, r l = 1 k to 2.5 v; ad8187: v s = 5 v, v ref = 2.5 v, r l = 150 to 2.5 v; unless otherwise noted.) parameter conditions min typ max unit dynamic performance e3 db bandwidth (small signal) v out = 200 mv p-p 1000/1000 mhz e3 db bandwidth (large signal) v out = 2 v p-p 450/480 mhz 0.1 db flatness v out = 200 mv p-p 90/85 mhz slew rate (10% to 90% rise time) v out = 2 v p-p, r l = 150 1600/1500 v/ s settling time to 0.1% v in = 1 v step, r l = 150 6/7.5 ns noise/distortion performance differential gain 3.58 mhz, r l = 150 0.05/0.05 % differential phase 3.58 mhz, r l = 150 0.05/0.05 degrees all hostile crosstalk 5 mhz e84/e78 db 100 mhz e52/e48 db channel-to-channel crosstalk, rti 5 mhz e90/e85 db off isolation 5 mhz e84/e95 db voltage noise, rti f = 100 khz to 100 mhz 7/9 nv/ hz cence e n 0.3/0.6 % voltage gain error matching channel a to channel b 0.04/0.04 0.2/0.2 % v ref gain error 1 k l oad 0.04 0.6 % input offset voltage 0.2/0.5 6.5/7.0 mv t min to t max 8.0 mv input offset voltage matching channel a to channel b 0.2/0.2 5.0/5.5 mv input offset drift 10/5 v/?c input bias current 1.5/1.5 4/4 a v ref bias current (for ad8187 only) 1.0 a input characteristics input resistance @100 khz 1.8/1.3 m input capacitance 0.9/1.0 pf input voltage range (about midsupply) in0a, in0b, in1a, in1b, in2a, in2b 1.2/ 1.2 v v ref +0.9, e1.2 v output characteristics output voltage swing r l = 1 k 3.1/2.8 3.2/3.0 v p-p r l = 150 2.8/2.5 3.0/2.7 v p-p short circuit current 85 ma output resistance enabled @ 100 khz 0.2/0.35 disabled @ 100 khz 1000/600 k output capacitance disabled 1.5/2.0 pf power supply operating range 3.5 5.5 v power supply rejection ratio +psrr, v cc = 4.5 v to 5.5 v, v ee = 0 v e72/e61 db epsrr, v ee = e0.5 v to +0.5 v, v cc = 5.0 v e76/e72 db quiescent current all channels on 18.5/19.5 21.5/22.5 ma all channels off 3.5/4.5 4.5/5.5 ma t min to t max , all channels on 15 23 ma ad8186/ad8187
rev. a ad8186/ad8187 e3e parameter conditions min typ max unit switching characteristics channel-to-channel switching time 50% logic to 50% output settling, ina = +1 v, inb = e1 v 3.6/4 ns enable to channel on time 50% logic to 50% output settling, input = 1 v 4/3.8 ns disable to channel off time 50% logic to 50% output settling, input = 1 v 17/5 ns channel switching transient (glitch) all channels grounded 21/45 mv output enable transient (glitch) all channels grounded 64/118 mv digital inputs logic 1 voltage sel a/ b e se b e c se b e c se b e a operating temperature range temperature range operating (still air) e40 +85 ?c ja operating (still air) 85 ?c/w jc operating 20 ?c/w specifications subject to change without notice. ad8186/ad8187
rev. a e4e ad8186/ad8187 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad8186/ad8187 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings 1, 2, 3, 4 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v dv cc to d gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v dv cc to v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 v v cc to d gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 v in0a, in0b, in1a, in1b, in2a, in2b, v ref . . . v ee v in v cc sel a/ b e n n cc sc s cc s c nes s e s c ss c c c/w is on a 4-layer board (2s 2p). maximum power dissipation the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150?c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175?c for an extended period can result in device failure. while the ad8186/ad8187 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150?c) is not exceeded under all conditions. to ensure proper operation, it is necessary to observe the maximum power derating curves shown in figure 2. pin configuration in0a d gnd v ref out 0 out 1 out 2 in1a in2a in2b in1b in0b v cc v ee v ee v ee v cc oe sel a/ b v ee v cc v cc v cc v ee dv cc 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad8186/ ad8187 top view (not to scale) ambient temperature ( c) e50 e40 maximum power dissipation (w) 1.0 0.5 1.5 0 2.0 2.5 e30 e20 e10 0 10 20 30 40 50 60 70 80 90 figure 2. maximum power dissipation vs. temperature ordering guide model temperature range package description package option ad8186aru e40?c to +85?c 24-lead thin shrink small outline package (tssop) ru-24 ad8186aru-reel e40?c to +85?c 13 " reel tssop ru-24 ad8186aru-reel 7 e40?c to +85?c 7 " reel tssop ru-24 ad8187aru e40?c to +85?c 24-lead thin shrink small outline package (tssop) ru-24 ad8187aru-reel e40?c to +85?c 13 " reel tssop ru-24 ad8187aru-reel 7 e40?c to +85?c 7 " reel tssop ru-24 AD8186-EVAL evaluation board ad8187-eval evaluation board
rev. a ad8186/ad8187 e5e t ypical performance characteristicse frequency (mhz) flatness (db) 0.1 1.0 10.0 100.0 1000.0 0.6 0.5 0.4 0.3 0.2 0.1 e0.1 e0.2 e0.3 0 gain (db) 3 2 1 0 e1 e2 e3 e4 e5 e6 dut 976 50 52.3 flatness gain 10000.0 tpc 1. ad8186 frequency response, v out = 200 mv p-p, r l = 1 k frequency (mhz) gain (db) 0.1 1.0 10.0 100.0 1000.0 1 0 e1 e2 e3 e4 e5 e6 e7 e8 dut 150 976 50 52.3 tpc 2. ad8186 frequency response, v out = 2 v p-p, r l = 1 k frequency (mhz) normalized gain (db) 0.1 1.0 10.0 100.0 1000.0 1 0 e1 e2 e3 e4 e5 e6 +85 c +25 c e40 c dut 150 976 50 52.3 tpc 3. ad8186 large signal bandwidth vs. temperature, v out = 2 v p-p, r l = 1 k frequency (mhz) 0.1 1.0 10.0 100.0 1000.0 10000.0 normalized gain (db) 1 0 e1 e2 e3 e4 e5 e6 flatness gain normalized flatness (db) 0.5 0.4 0.3 0.2 0.1 0 e0.1 e0.2 tpc 4. ad8187 frequency response, v out = 200 mv p-p, r l = 150 frequency (mhz) normalized gain (db) 0.1 1.0 10.0 100.0 1000.0 1 0 e1 e2 e3 e4 e5 e6 tpc 5. ad8187 frequency response, v out = 2 v p-p, r l = 150 frequency (mhz) normalized gain (db) 0.1 1.0 10.0 100.0 1000.0 1 0 e1 e2 e3 e4 e5 e6 +25 c e40 c +85 c tpc 6. ad8187 large signal bandwidth vs. temperature, v out = 2 v p-p, r l = 150
rev. a e6e ad8186/ad8187 frequency (mhz) crosstalk (db) 0.1 11 0 100 1000 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 tpc 7. ad8186 all hostile crosstalk* vs. frequency frequency (mhz) crosstalk (db) 0.1 1.0 10.0 100.0 1000.0 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 tpc 8. ad8186 adjacent channel crosstalk* vs. frequency frequency (mhz) off isolation (db) 0 10 100 1000 e30 e40 e50 e60 e70 e80 e90 e100 e10 e20 0 tpc 9. ad8186 off isolation* vs. frequency * all hostile crosstalk?drive all ina, listen to output with inb selected. adjacent channel crosstalk?drive one ina, listen to an adjacent output with inb selected. off isolation?drive inputs with oe tied low. frequency (mhz) crosstalk (db) 0.1 1.0 10.0 100.0 1000.0 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 tpc 10. ad8187 all hostile crosstalk* vs. frequency frequency (mhz) crosstalk (db) 0.1 1.0 10.0 100.0 1000.0 0 e10 e20 e30 e40 e50 e60 e70 e80 e90 e100 e110 e120 tpc 11. ad8187 adjacent channel crosstalk* vs. frequency frequency (mhz) off isolation (db) 11 0 100 1000 e40 e120 e20 0 e100 e60 e80 e10 e30 e50 e70 e90 e110 tpc 12. ad8187 off isolation* vs. frequency
rev. a ad8186/ad8187 e7e e100 e90 e80 e70 e60 e50 e40 e30 e20 e10 0 1 10 100 distortion (dbc) frequency (mhz) third second tpc 13. ad8186 harmonic distortion vs. frequency v out = 2 v p-p, r l = 150 frequency (mhz) 0.01 0.10 1 10 100 psrr (db) e90 e80 e70 e60 e50 e40 e30 e20 e10 0 epsrr + psrr tpc 14. ad8186 psrr vs. frequency, r l = 150 frequency (mhz) noise (nv/ hz) 0.01 0.10 1 10 100 20 10 8 6 4 2 0 10000 18 16 14 12 1000 tpc 15. ad8186 input voltage noise vs. frequency frequency (mhz) 1 10 100 e100 e90 e80 e70 e60 e50 e40 e30 e20 e10 0 distortion (dbc) third second tpc 16. ad8187 harmonic distortion vs. frequency v out = 2 v p-p, r l = 150 frequency (mhz) 0.01 0.10 1 10 100 psrr (db) e80 e70 e60 e50 e40 e30 e20 e10 0 epsrr + psrr tpc 17. ad8187 psrr vs. frequency, r l = 150 frequency (mhz) noise (nv/ hz) 0.01 0.1 1 10 100 20 10 8 6 4 2 0 10000 18 16 14 12 1000 tpc 18. ad8187 input voltage noise vs. frequency
rev. a e8e ad8186/ad8187 frequency (mhz) impedance (k ) 0.1 1 10 100 10000 10 1 0.1 1000 100 1000 tpc 19. ad8186 input impedance vs. frequency frequency (mhz) impedance ( ) 0.1 1 10 100 1000 1 0.1 100 10 1000 tpc 20. ad8186 enabled output impedance vs. frequency frequency (mhz) impedance (k ) 0.1 1.0 10.0 100.0 10000 10 1 0.1 1000 100 1000.0 tpc 21. ad8186 disabled output impedance vs. frequency frequency (mhz) impedance (k ) 0.1 1.0 10.0 100.0 10000 10 1 0.1 1000 100 1000.0 tpc 22. ad8187 input impedance vs. frequency frequency (mhz) impedance ( ) 0.1 1.0 10.0 100.0 1000 1 0.1 100 10 1000.0 tpc 23. ad8187 enabled output impedance vs. frequency frequency (mhz) impedance ( ) 0.1 1.0 10.0 100.0 10000 10 1 0.1 1000 100 1000.0 tpc 24. ad8187 disabled output impedance vs. frequency
rev. a ad8186/ad8187 e9e time (ns) output voltage (v) 0510 15 20 3.30 2.80 2.30 input voltage (v) 2.80 2.50 2.00 1.80 input output 2.70 2.60 2.40 2.30 2.20 2.10 1.90 25 tpc 25. ad8186 small signal pulse response, v out = 200 mv p-p, r l = 1 k time (ns) output voltage (v) 0510 15 20 5.0 4.5 input voltage (v) 2.0 4.0 3.5 3.0 2.5 2.0 1.5 1.0 1.5 1.0 0.5 0 e0.5 e1.0 2.5 3.0 input output 25 tpc 26. ad8186 video signal pulse response, v out = 700 mv p-p, r l = 1 k time (ns) output voltage (v) 0510 15 20 7.0 6.5 input voltage (v) 2.0 6.0 5.5 5.0 4.5 4.0 3.5 3.0 1.5 1.0 0.5 0 e0.5 e1.0 2.5 3.0 e1.5 e2.0 3.5 4.0 2.5 2.0 1.5 1.0 input output 25 tpc 27. ad8186 large signal pulse response, v out = 2 v p-p, r l = 1 k time (ns) output voltage (v) 05 10 3.2 3.1 input voltage (v) 2.5 3.0 2.9 2.8 2.7 2.6 2.4 2.3 2.2 2.1 2.0 2.6 1.9 1.8 2.7 2.8 2.5 2.4 2.3 2.2 input output 15 20 25 tpc 28. ad8187 small signal pulse response, v out = 200 mv p-p, r l = 150 k time (ns) output voltage (v) 05 10 6.0 5.5 input voltage (v) 2.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 e0.5 e1.0 3.5 4.0 2.0 1.5 1.0 input output 15 20 5.0 25 tpc 29. ad8187 video amplitude pulse response, v out = 1.4 v p-p, r l = 150 k time (ns) output voltage (v) 0 6.0 5.5 input voltage (v) 2.5 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 3.0 e0.5 e1.0 3.5 4.0 2.0 1.5 1.0 input output 5.0 e1.5 0.5 e2.0 0 5101520 25 tpc 30. ad8187 large signal pulse response, v out = 2 v p-p, r l = 150 k
rev. a e10e ad8186/ad8187 time (2ns/div) output (1mv/div) t 0 t settled tpc 31. ad8186 settling time (0.1%), v out = 2 v step, r l = 1 k time (ns) output amplitude (v) 0510 15 20 6.0 select a/ b pulse amplitude (v) 5.5 4.5 3.5 2.5 0.8 0.3 e0.8 e1.3 1.3 1.8 e1.8 e2.3 2.3 1.5 1.0 sel a/ b output e2.8 e0.3 2.0 3.0 4.0 5.0 25 tpc 32. ad8186 channel-to-channel switching time, v out = 2 v p-p, ina = 3.5 v, inb = 1.5 v time (ns) output amplitude (v) 0510 15 20 2.8 select a/ b pulse amplitude (v) 2.7 2.6 2.5 2.4 output e1.0 sel a/ b 25 30 35 40 45 2.9 3.0 e0.5 0 0.5 1.0 1.5 2.0 50 tpc 33. ad8186 channel switching transient (glitch), ina = inb = 0 v time (2ns/div) output (1mv/div) t 0 t settled tpc 34. ad8187 settling time (0.1%), v out = 2 v step, r l = 150 time (ns) output amplitude (v) 0510 15 20 4.0 select a/ b pulse amplitude (v) 2.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 e0.5 e1.0 e1.5 e2.0 1.5 1.0 e2.5 sel a/ b output 4.5 5.0 5.5 25 tpc 35. ad8187 channel-to-channel switching time, v out = 2 v p-p, ina = 3.0 v, inb = 2.0 v time (ns) output amplitude (v) 05 10 15 20 2.80 select a/ b pulse amplitude (v) 1.50 2.70 2.60 0.50 e0.50 2.00 2.50 2.40 output e1.00 sel a/ b 25 30 35 40 45 1.00 0 2.90 3.00 50 tpc 36. ad8187 channel switching transient (glitch), ina = inb = v ref = 0 v
rev. a ad8186/ad8187 e11e time ( ns ) output amplitude (v) 04080 120 160 oe pulse amplitude (v) 2.0 1.5 1.0 0.5 0 e0.5 e1.0 output e1.5 5.0 4.0 3.0 2.0 5.5 4.5 3.5 2.5 oe 200 tpc 37. ad8186 enable on/off time, v out = 0 v to 1 v time (ns) output amplitude (v) 0510 15 20 3.0 2.7 2.4 oe pulse amplitude (v) 1.5 1.0 0.5 0 2.5 25 30 35 40 45 output oe 2.9 2.8 2.6 50 tpc 38. ad8186 channel enable/disable transient (glitch) time e ns output amplitude (v) 04080 120 160 oe pulse amplitude (v) 2.0 1.5 1.0 0.5 0 e0.5 e1.0 e1.5 output e2.0 6.0 5.0 4.0 3.0 2.0 5.5 4.5 3.5 2.5 oe 200 tpc 39. ad8187 enable on/off time, v out = 0 v to 1 v time (ns) output amplitude ( v ) 010203040 oe pulse amplitude (v) 2.00 1.50 1.00 0.50 0 e0.50 output e1.00 2.70 2.80 2.60 2.50 2.40 oe 515253545 2.90 3.00 50 tpc 40. ad8187 channel enable/disable transient (glitch)
rev. a e12e ad8186/ad8187 theory of operation the ad8186 (g = +1) and ad8187 (g = +2) are single-supply, triple 2:1 multiplexers with ttl compatible global input switch- ing and output-enable control. optimized for select ing between two rgb (red, green, blue) video sources, the devices have high peak slew rates, maintaining their bandwidth for large signals. additionally, the multiplexers are compensated for high phase margin, minimizing overshoot for good pixel resolution. the multiplexers also have respectable video specifications and are superior for switching ntsc or pal composite signals. the multiplexers are organized as three independent channels, each with two input transconductance stages and one output transimpedance stage. the appropriate input transconductance stages are selected via one logic pin (sel a/ b n b e ) with low differential gain and phase errors while consuming relatively little power. careful chip layout and biasing result in excellent crosstalk isolation between channels. high impedance, output disable feature, and off isolation the output-enable logic pin (oe) controls whether the three outputs are enabled or disabled to a high impedance state. the high impedance disable allows larger matrices to be built by busing the outputs together. in the case of the ad8187 (g = +2), a feedback isolation scheme is used so that the impedance of the gain-of-two feedback network does not load the output. when not in use, the outputs can be disabled to reduce power consumption. the reader may have noticed that the off isolation performance of the signal path is dependent upon the value of the load resistor, r l . for calculating off isolation, the signal path may be modeled as a simple high-pass network with an effective capacitance of 3 ff. off isolation will improve as the load resistance is decreased. in the case of the ad8186, off isolation is specified with a 1 k load. however, a practical application would likely gang the outputs of multiple muxes. in this case, the proper load resistance for the off isolation calculation is the output impedance of an enabled ad8186, typically less than a 10th of an ohm. full power bandwidth vs. e3 db large signal bandwidth note that full power bandwidth for an undistorted sinusoidal signal is often calculated using the peak slew rate from the equation full power bandwidth = peak slew rate sinusoid amplitude 2 the peak slew rate is not the same as the average slew rate. the average slew rate is typically specified as the ratio v t out measured between the 20% to 80% output levels of a suffi- ciently large output pulse. for a natural response, the peak slew rate may be 2.7 times larger than the average slew rate. there- fore, calculating a full power bandwidth with a specified average slew rate will give a pessimistic result. in specifying the large signal performance of these multiplexers, we?ve published the large-signal bandwidth, the average slew rate, and the measure- ments of the total harmonic distortion. (large signal bandwidth is defined as the e3 db point measured on a 2 v p-p output sine wave.) s pecifying these three aspects of the signal path?s large signal dynamics allows the user to predict system behavior for either pulse or sinusoid waveforms. single-supply considerations dc-coupled inputs, integrated reference buffers, and selecting the v ref level on the ad8187, (g = +2) the ad8186 and ad8187 offer superior large signal dynamics. the trade-off is that the input and output compliance is limited to ~1.3 v from either rail when driving a 150 load. these sections address some challenges of designing video systems within a single 5 v supply. the ad8186 the ad8186 is internally wired as a unity-gain follower. its inputs and outputs can both swing to within ~1.3 v of either rail. this affords the user 2.4 v of dynamic range at input and output, which should be enough for most video signals, whether the inputs are ac- or dc-coupled. in both cases, the choice of output termination voltage will determine the quiescent load current. for improved supply rejection, the v ref pin should be tied to an ac ground (the more quiet supply is a good bet). internally, the v ref pin connects to one terminal of an on-chip capacitor. the capacitor?s other terminal connects to an internal node. the consequence of building this bypass capacitor on-chip is twofold. first, the v ref p in on the ad8186 draws no input bias current. (contrast this to the case of the ad8187, where the v ref pin typically draws 2 a of input bias current). second, on the ad8186, the v ref pin may be tied to any voltage within the supply range. in0a in0b in1b in1a in2a in2b ad8186 out0 out1 out2 mux system bias reference internal cap c_bypass d irect connection to any quiet ac ground (for example, gnd, v cc , v ee) v ref figure 3. v ref pin connection for ad8186 (differs from ad8187)
rev. a ad8186/ad8187 e13e the ad8187 the ad8187 uses on-chip feedback resistors to realize the gain- of-two function. to provide low crosstalk and a high output impedance when disabled, each set of 500 feedback resistors is terminated by a dedicated reference buffer. a reference buffer is a high speed op amp configured as a unity-gain follower. the three reference buffers, one for each channel, share a single, high impedance input, the v ref pin (see figure 4). v ref input bias current is typically less than 2 a. a0 b0 v ref 5v 5v 5v gbuf 0 5v gbuf 1 5v gbuf 2 500 500 out 0 500 500 500 500 vf-1 vf-2 1 vfo out1 out2 figure 4. conceptual diagram of a single multiplexer channel, g = +2 this configuration has a few implications for single-supply operation: 1) on the ad8187, v ref may not be tied to the most negative analog supply, v ee . limits on reference voltage (ad8187, see figure 5): vvvvv vv vo n v / v supplies ee ref cc ref +<< << 13 16 13 34 0 5 .e. .. a0 v ref 5v 5v out 0 5v 5v 1.3v 1.3v 1.6v 1.3v v out v o_max = 3.7v v o_max = 3.4v v o_min = 1.3v v o_min = 1.3v v ref gnd gnd figure 5. output compliance of main amplifier channel and ground buffer 2) signal at the v ref pin appears at each output. therefore, v ref should be tied to a well bypassed, low impedance source. using superposition, it is easily shown that vvv out in ref = 2e 3) to maximize the output dynamic range, the reference voltage should be chosen with some care. for example, consider amplifying a 700 mv video signal with a sync pulse 300 mv below black level. the user might decide to set v ref at black level to preferentially run video signals on the faster npn transistor path. the ad8186 would, in this case, allow a reference voltage as low as 1.3 v + 300 mv = 1.6 v. if the ad8187 is used, the sync pulse would be amplified to 600 mv. therefore, the lower limit on v ref becomes 1.3 v + 600 mv = 1.9 v. for routing rgb video, an advantageous configuration would be to employ +3 v and e2 v supplies, in which case v ref could be tied to ground. if system considerations prevent running the multiplexer on split supplies, a false ground reference should be employed. a low impedance reference may be synthesized with a second opera- tional amplifier. alternately, a well bypassed resistor divider may serve. refer to the application section for further explana- tion and more examples. v ref 1 f 5v gnd op21 100k 10k 0.022 f 100 1 f from 1992 adi amplifier applications guide figure 6a. synthesis of a false ground reference v ref 1 f 5v 10k 10k cap must be large enough to absorb transient currents with minimum bounce. figure 6b. alternate method for synthesis of a false ground reference high impedance disable both the ad8186 and the ad8187 may have their outputs disabled to a high impedance state. in the case of the ad8187, the reference buffers also disable to a state of high output impedance. this feature prevents the feedback network of a disabled channel from loading the output, which is valuable when busing together the outputs of several muxes.
rev. a e14e ad8186/ad8187 ac-coupled inputs (dc restore before mux input) using ac-coupled inputs presents an interesting challenge for video systems operating from a single 5 v supply. in ntsc and pal video systems, 700 mv is the approximate difference between the maximum signal voltage and black level. it is assumed that sync has been stripped. however, given the two pathological cases shown in figure 7, a dynamic range of twice the maximum signal swing is required if the inputs are to be ac-coupled. a possible solution would be to use a dc restore circuit before the mux. v ref + 700mv v avg +5 v v signal gnd v input = v ref + v signal v ref ~ v avg v ref is a dc voltage set by the resistors black line with white pixel e700mv white line with black pixel v avg v ref figure 7. pathological case for input dynamic range tolerance to capacitive load op amps are sensitive to reactive loads. a capacitive load at the output appears in parallel with an effective resistance of r eff = ( r l r o ), where r l is the discrete resistive load, and r o is the open- loop output impedance, approximately 15 for these muxes. the load pole, at f load = 1/(2 r eff c l ), can seriously degrade phase margin and therefore stability. the old workaround is to place a small series resistance directly at the output to isolate the load pole. while effective, this ruse also affects the dc and termina- tion characteristics of a 75 system. the ad8186 and ad8187 are built with a variable compensation scheme that senses the output reactance and trades bandwidth for phase margin, ensuring faster settling and lower overshoot at higher capacitive loads. secondary supplies and supply bypassing the high current output transistors are given their own supply pins (pins 15, 17, 19, and 21) to reduce supply noise on-chip and to improve output isolation. since these secondary, high current supply pins are not connected on-chip to the primary analog supplies (v cc /v ee , pins 6, 7, 9, 11, 13, and 24), some care should be taken to ensure that the supply bypass capacitors are connected to the correct pins. at a minimum, the primary sup plies should be bypassed. pin 6 and pin 7 may be a convenient place to accomplish this. stacked power and ground planes could be a convenient way to bypass the high current supply pins. in0a d gnd v ref out 0 out 1 out 2 in1a in2a in2b in1b in0b v cc v ee v ee v ee v cc oe sel a/ b v ee v cc v cc v cc v ee dv cc mux0 mux1 mux2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 1 f 0.1 f figure 8. detail of primary and secondary supplies split-supply operation operating from split supplies (e.g., +3 v/e2 v or 2.5 v) simpli- fies the selection of the v ref voltage and load resistor termination voltage. in this case, it is convenient to tie v ref to ground. the logic inputs are level shifted internally to allow the digital supplies and logic inputs to operate from 0 v and 5 v when powering the analog circuits from split supplies. the maximum voltage differ ence between dv cc and v ee must not exceed 8 v (see figure 9). dv cc (+5) d gnd split-supply operation digital supplies (0v) 8v max analog supplies (+2.5) ( e2.5) v cc v ee figure 9. split-supply operation
rev. a ad8186/ad8187 e15e application single-supply operation the ad8186/ad8187 are targeted mainly for use in single- supply 5 v systems. for operating on these supplies, both v ee and d gnd should be tied to ground. the control logic pins will be referenced to ground. normally, the dv cc supply should be set to the same positive supply as the driving logic. for dc-coupled single-supply operation, it is necessary to set an appropriate input dc level that is within the specified range of the amplifier. for the unity-gain ad8186, the output dc level will be the same as the input, while for the gain-of-two ad8187, the v ref input can be biased to obtain an appropriate output dc level. figure 10 shows a circuit that provides a gain-of-two and is dc- coupled. the video input signals must have a dc bias from their source of approximately 1.5 v. this same volt- age is applied to v ref of the ad8187. the result is that when the video signal is at 1.5 v, the output will also be at the same voltage. this is close to the lower dynamic range of both the input and the output. when the input goes most positive, which is 700 mv above the black level for a standard video signal, it reaches a value of 2.2 v and there is enough headroom for the signal. on the output side, the magnitude of the signal will change by 1.4 v, which will make the maximum output voltage 2.2 v + 1.4 v = 3.6 v. this is just within the dynamic range of the output of the part. ac coupling when a video signal is ac-coupled, the amount of dynamic range required to handle the signal can potentially be double that required for dc-coupled operation. for the unity-gain ad8186, t here is still enough dynamic range to handle an ac-coupled, standard video signal with 700 mv p-p amplitude. if the input is biased at 2.5 v dc, the input signal can potentially go 700 mv both above and below this point. the resulting 1.8 v and 2.2 v are within the input signal range for single 5 v operation. since the part is unity-gain, the outputs will follow the inputs, and there will be adequate range at the output as well. when using the gain-of-two ad8187 in a simple ac-coupled application, there will be a dynamic range limitation at the output caused by its higher gain. at the output, the gain-of-two will produce a signal swing of 1.4 v, but the ac coupling will double this required amount to 2.8 v. the ad8187 outputs can only swing from 1.4 v to 3.6 v on a 5 v supply, so there are only 2.2 v of dynamic signal swing available at the output. a standard means for reducing the dynamic range requirements of an ac-coupled video signal is to use a dc restore. this circuit works to limit the dynamic range requirements by clamping the black level of the video signal to a fixed level at the input to the amplifier. this prevents the video content of the signal from varying the black level as happens in a simple ac-coupled circuit. after ac coupling a video signal, it is always necessary to use a dc restore to establish where the black level is. usually, this appears at the end of a video signal chain. t his dc restore circuit needs to have the required accuracy for the system. it compen- sates for all the offsets of the preceding stages. therefore, if a dc restore circuit is to be used only for dynamic-range limiting, it does not require great dc accuracy. d gnd v ee red grn blu in2b in1b in0b in0a reda in1a grna in2a blua v ref 5v 1.5v 3.48k 1.5k blub grnb redb dv cc 3v to 5v black level typical output levels (all 3 outputs) 3.0v 1.4v max 1.5v black level 2.2v 1.5v 0.7v max typical input levels (all 6 outputs) sel a/ b oe 2 out0 out1 out2 v cc 5v ad8187 2 2 figure 10. dc-coupled (bypassing and logic not shown)
rev. a e16e ad8186/ad8187 a dc restore circuit using the ad8187 is shown in figure 11. two separate sources of rgb video are ac-coupled to the 0.1 f input capacitors of the ad8187. the input points of the ad8187 are switched to a 1.5 v reference by the adg786, which works in the following manner: the sel a/ b b e en zb hsync en z h n n z bs bs hsc e z cc eb e cc s e n b nb nb nb n e n n n b e bb nb eb cc se b e cc s sb s sb s sb n ss c en hsync n n e se b e ee n ccc
rev. a ad8186/ad8187 e17e evaluation board figure 12. component side board layout figure 13. circuit side board layout
rev. a e18e ad8186/ad8187 figure 14. component side silkscreen figure 15. circuit side silkscreen
rev. a ad8186/ad8187 e19e in0a d gnd v ref out 0 out 1 out 2 in1a in2a in2b in1b in0b v cc v ee v ee v ee v cc oe sel a/ b v ee v cc v cc v cc v ee dv cc 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 ad8186/ ad8187 dut c10 0.1 f c15 10 f v cc v cc r23 1k v cc w1 v cc r24 1k oe sel a/ b out 0 out 1 out 2 c7 0.1 f v cc r9 75 r10 * tbd r20 * tbd w2 c18 0.1 f c19 0.1 f c20 0.1 f r12 * tbd r14 * tbd v cc v cc v cc c12 0.1 f c17 0.1 f c16 10 f r13 75 r11 75 gnd1 gnd2 gnd3 gnd4 v ref r22 4.99k a gnd r4 75 a gnd c1 0.1 f r22 4.99k v ref r5 75 c4 0.1 f c14 0.01 f c24 0.1 f r16 4.99k v ref v ref in0a in1a in2a in2b in1b in0b cw v cc v ref c5 0.1 f v cc r6 75 v ref c6 0.1 f c13 10 f c3 0.1 f r17 4.99k r7 75 v ref c8 0.1 f r18 4.99k v ref c9 0.1 f r21 4.99k r3 75 r8 75 a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd a gnd r15 * tbd a gnd * r10, r12, r14, r15, and r20 not installed on evaluation board for test purposes. r1 is not used for ad8186. r1 figure 16. single-supply evaluation board
c02985e0e6/03(a) e20e ad8186/ad8187 revision history location page 6/03?data sheet changed from rev. 0 to rev. a. changes to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to tpcs 32, 35, and 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 outline dimensions 24-lead thin shrink small outline package [tssop] (ru-24) dimensions shown in millimeters 24 13 12 1 6.40 bsc 4.50 4.40 4.30 pin 1 7.90 7.80 7.70 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.75 0.60 0.45 8 0 seating plane compliant to jedec standards mo-153ad 0.10 coplanarity rev. a

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